1. Field of the Invention
The present invention generally relates to an image sensor, and more particularly to a process and structure of a non-self aligned back side illumination (BSI) CMOS image sensor.
2. Description of Related Art
The pixel size of a complementary metal oxide semiconductor (CMOS) image sensor (CIS) becomes smaller than ever to meet high resolution and low form factor (or physical dimensions) requirement, for example, for mobile devices. FIG. 1A shows a cross sectional view of a conventional photodiode along with a portion of a pixel circuit. The front side of silicon wafer receives light, and this type of CIS is commonly called the front side illumination (FSI) CIS. As the p-type implant 10 and the n-type implant 12 of the photodiode are masked defined, this type of FSI CIS is thus called the non-self aligned (non-SA) FSI CIS. One of the disadvantages of the non-SA FSI CIS is the overlap issue, in which the first overlap 100 between the p-type implant 10 and the transfer gate (Tx) 14 and the second overlap 120 between the n-type implant 12 and the transfer gate 14 cannot be precisely controlled. Specifically, the first overlap 100 provides low leakage dark current when the transfer gate 14 is off, and the second overlap 120 provides smooth charge transfer when the transfer gate 14 is on. FIG. 1B exemplifies a non-SA FSI CIS with narrow second overlap 120 due to misalignment 122. Accordingly, the performance of the pixels in the non-SA FSI CIS varies tremendously from column to column, wafer to wafer, and lot to lot.
FIG. 1C shows a cross sectional view of another conventional FSI CIS. The p-type implant 10 and the n-type implant 12 are aligned with the transfer gate 14, which is used as a mask, and this type of FSI CIS is thus called the self aligned (SA) FSI CIS. Compared to the non-SA FSI CIS (FIG. 1A), the SA FSI CIS may achieve consistent performance. However, it is difficult to have a large margin on the second overlap 120 between the n-type implant 12 and the transfer gate 14 due to some design constrains such as the photodiode depth, shape, blue response or transfer gate height. Accordingly, the tiny second overlap 120 may be easily affected by other implants, particularly when the pixel size is very small, thereby complicating the process optimization.
In order to solve the overlap issue discussed above, there are some schemes disclosed to make the second overlap 120 between the n-type implant 12 and the transfer gate 14 sufficiently large so that the overlap variation becomes relatively small or/and the performance of the transfer gate 14 does not change due to overlap variation. FIG. 2A shows a cross sectional view of a conventional FSI CIS before applying the schemes, FIG. 2B shows a cross sectional view of a FSI CIS after applying the first scheme, and FIG. 2C shows a cross sectional view of a FSI CIS after applying the second scheme.
In the first scheme, as shown in FIG. 2B which is to be compared to FIG. 2A, the transfer gate 14 is kept unchanged, but the edge of the n-type implant 12 is extended into the transfer gate 14 area toward the floating diffusion (FD) 16. However, according to this scheme, the effective transfer gate length 140 becomes shorter, thereby increasing leakage current or even resulting in punch through between the n-type implant 12 and the floating diffusion 16.
In the second scheme, as shown in FIG. 2C which is to be compared to FIG. 2A, the n-type implant 12 is kept unchanged, but the edge of the transfer gate 14 is extended toward the photodiode (i.e., the p-type implant 10 and the n-type implant 12). However, according to this scheme, the effective area (or optical fill factor) for receiving incoming light becomes smaller, thereby degrading quantum efficiency (QE).
For the reason that conventional CIS, either non-SA FSI CIS or SA FSI CIS, could not effectively solve the overlap issue, a need has arisen to propose a novel CIS that has better performance than the conventional CIS.